Principal VLSI Design Engineer

Full Chip Integration: Drive the full chip integration activities involving Die Architecture, Die size estimation, Floorplan and module placement to achieve optimal die are meeting all design constraints.

Power Distribution & Floorplanning: Analyze and implement full-chip power distribution strategies and floorplanning optimization to ensure efficient electrical performance, minimize parasitics, and reduce die size.

Cross-Functional Collaboration: Work closely with design and process engineering teams across multiple sites to resolve issues, align methodologies, and drive project success while maintaining high standards of accuracy and consistency.